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Osaka, Japan – Industrials Devices Company,Panasonic Corporation has developed the New Power CSP MOSFET semiconductor.
High power density and better efficiency are constantly required by power designers. Power management applications need cost-effective solutions that minimize board space while increasing efficiency and thermal dissipation.Panasonic Corporation launched new MOSFET family utilizing a new PMCP package to help designers meet these power design challenges.
FJ3P02100L and FK3P02110L is available in October 2012 and so is FK3P03240L in March 2013.
This MOSFET family is optimized for load switches that combine low RDS(on) in a smaller form factor, reducing the power management system size and minimizing power consumption to increase power efficiency.
This MOSFET family is also a perfect fit for lithium ion battery applications where the low RDS(on) is a must. Using contact pads instead of pins or wires deliver the lowest RDS(on) that minimize the power dissipation and maximize the battery life.
Package size and thermal dissipation are directly proportional. As the package size decreases, the thermal dissipation also decreases. With the industry's first ultra-small PMCP package with high thermal capability, this new power MOSFET has reduced the size by 46%*1, become thinner by 67%*1 while improving the thermal dissipation capability by 5%*1, that leads to high-density mounting and miniaturizing power circuits.
A power MOSFET, which switches a current on and off by controlling the gate voltage, encounters resistance while current flows through it. In order to increase the current, lower resistance is required. In addition, the value of the resistance varies with the size of the cell. Therefore, we have reduced the resistance (RDS(on)) by 47%*1 over the same sized conventional chip. The power loss has been reduced when current flows through MOSFET significantly, thus achieving longer battery life and power savings.
Our thermal design utilizes a frame structure to optimize thermal dissipation from the chip to both the PCB and air; a higher thermal dissipation over our conventional product has been achieved while achieving small size and low-profile.
Normally, in an N-ch power MOSFET, current flows from the substrate to the channel. Increasing the number of cells by using a 110nm fine process technology reduces the resistance of the channel. In addition, using wafer thinning technology reduces the resistance of the substrate. Consequently, we have reduced the RDS(on) by 47%*1 versus the conventional solutions.
MP products: October 2012
Samples: Please contact your local sales office
|Drain-Source voltage||-20 V||24 V||30 V|
|Gate-Source voltage||±8 V||±12 V||±20 V|
|Drain current||4.4 A||3.0 A||14 A|
|12.0 mΩ (typ.)
@VGS = 2.5 V
|12.5 mΩ (typ.)
@VGS = 2.5 V
|3.5 mΩ (typ.)
@VGS = 10V
|Input capacitance||3000 pF (typ.)||1500 pF (typ.)||1550 pF (typ.)|
(Vertical × Horizontal × Height)
|Mass production||Oct. 2012||Oct. 2012||March 2013|
[Description of words]
Metal-Oxide-Semiconductor Field-Effect Transistor, and refers to a field effect transistor using an oxide layer to isolate the gate.
 Load switch
A switch to control on/off of a line supplying a power to larger circuits.
A resistance between drain and source of MOSFET while it is in an on state.
The content in the following news releases is accurate at the time of publication but may be subject to change without notice.
Please note therefore that these documents may not always contain the most up-to-date information.
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